In digital design, it may be necessary to convert data from a source input bus of ‘M’ bits to a destination output bus of ‘N’ bits, where M and N are of arbitrary widths. In many cases, the arbitrary widths may not be related. That is, the output width may not be a multiple of the input width. Methods for processing data generally involve buffering a multiple of M-bits of data in order to obtain N bits which is greater than M bits of data, and then use a technique to select the appropriate output data. The output data may be multiplexed to properly select the correct output data bits. Control logic is required to generate the data selection, such as through a state-machine using the lowest common denominator, a lookup-table based implementation. However, such conventional methods only address a single conversion, and each design must be re-analyzed for each new M and N value. Further, such conventional methods may not be optimal for devices having certain architectures, such as devices having programmable logic.